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Found 7 papers, 3 papers with code
TabConv: Low-Computation CNN Inference via Table Lookups
TabConv preserves over 93% of the original model's performance while reducing arithmetic operations by 36. 5%, 25. 8%, and 99. 4% for ResNet-18 on CIFAR-10, CIFAR-100, and MNIST, respectively, 35. 6% and 99. 3% for ResNet-34 on CIFAR-10 and MNIST, and 98. 9% for NIN on MNIST, achieving low-computation inference.
PaCKD: Pattern-Clustered Knowledge Distillation for Compressing Memory Access Prediction Models
Deep neural networks (DNNs) have proven to be effective models for accurate Memory Access Prediction (MAP), a critical task in mitigating memory latency through data prefetching.
ME-ViT: A Single-Load Memory-Efficient FPGA Accelerator for Vision Transformers
We evaluate ME-ViT on systolic array sizes of 32 and 16, achieving up to a 9. 22$\times$ and 17. 89$\times$ overall improvement in memory bandwidth, and a 2. 16$\times$ improvement in throughput per DSP for both designs over state-of-the-art ViT accelerators on FPGA.
Attention, Distillation, and Tabularization: Towards Practical Neural Network-Based Prefetching
DART accelerates the large model inference by 170x and the distilled model by 9. 4x.
Phases, Modalities, Temporal and Spatial Locality: Domain Specific ML Prefetcher for Accelerating Graph Analytics
Our predictors achieve 6. 80-16. 02% higher F1-score for delta and 11. 68-15. 41% higher accuracy-at-10 for page prediction compared with LSTM and vanilla attention models.
TransforMAP: Transformer for Memory Access Prediction
Data Prefetching is a technique that can hide memory latency by fetching data before it is needed by a program.
Fine-Grained Address Segmentation for Attention-Based Variable-Degree Prefetching
To reduce vocabulary size, we use fine-grained address segmentation as input.
