FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications

no code implementations • 5 Jun 2020 • Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei zhang, Shaojie Shen

To reduce the design effort and achieve the right balance, we propose FP-Stereo for building high-performance stereo matching pipelines on FPGAs automatically.

C++ code Depth Estimation +1

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

no code implementations • 6 May 2019 • Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei zhang

Early and accurate congestion estimation is of great benefit to guide the optimization in HLS and improve the efficiency of implementation.

BIG-bench Machine Learning Face Detection +1