Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

no code implementations • 29 Apr 2021 • Vivek Saraswat, Ajinkya Gorad, Anand Naik, Aakash Patil, Udayan Ganguly

In this work, we analyze the role of synaptic orders namely: {\delta} (high output for single time step), 0th (rectangular with a finite pulse width), 1st (exponential fall) and 2nd order (exponential rise and fall) and synaptic timescales on the reservoir output response and on the TI-46 spoken digits classification accuracy under a more comprehensive parameter sweep.

General Classification Spoken Digits Recognition

ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS

no code implementations • 4 Dec 2019 • Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Zhang Lei, Aakash Patil, Arindam Basu

However, on the detection of anomalies, the complexity of the network and computing precision are adaptively increased for accurate predictions.

Anomaly Detection Edge-computing +1

Hardware Architecture for Large Parallel Array of Random Feature Extractors applied to Image Recognition

no code implementations • 24 Dec 2015 • Aakash Patil, Shanlan Shen, Enyi Yao, Arindam Basu

We demonstrate a low-power and compact hardware implementation of Random Feature Extractor (RFE) core.

Total Energy