no code implementations • 19 Aug 2022 • Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
Furthermore, we show that our approach can reduce communication size by up to 92. 4% compared with a baseline ResNet model using CIFAR-10 dataset.
no code implementations • 27 Jul 2021 • Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
It is implemented on Xilinx ZCU104 board and evaluated in terms of domain adaptation accuracy, inference speed, FPGA resource utilization, and speedup rate compared to a software counterpart.