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A Cost-Efficient FPGA Implementation of Tiny Transformer Model using Neural ODE
To mitigate the computational complexity, recently, a hybrid approach has been proposed, which uses ResNet as a backbone architecture and replaces a part of its convolution layers with an MHSA (Multi-Head Self-Attention) mechanism.
An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm
A graph embedding is an emerging approach that can represent a graph structure with a fixed-length low-dimensional vector.
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs
It is implemented on Xilinx ZCU104 board and evaluated in terms of domain adaptation accuracy, inference speed, FPGA resource utilization, and speedup rate compared to a software counterpart.
An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm
In this paper, we propose a resource-efficient FPGA implementation for accelerating scan matching computations, which typically cause a major bottleneck in 2D LiDAR SLAM methods.
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