A 4x32Gb/s 1.8pJ/bit Collaborative Baud-Rate CDR with Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution

no code implementations • 10 Apr 2024 • Jihee Kim, Jia Park, Jiwon Shin, Hanseok Kim, Kahyun Kim, Haengbeom Shin, Ha-Jung Park, Woo-Seok Choi

To this end, a fractional divider controlled by CDR is placed close to the global phase locked loop.

A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface with XTalk Minimizing Affine Signaling for Next-Generation HBM with High Interconnect Density

no code implementations • 8 Apr 2024 • Hyunjun Park, Jiwon Shin, Hanseok Kim, Jihee Kim, Haengbeom Shin, TaeHoon Kim, Jung-Hun Park, Woo-Seok Choi

This paper presents an I/O interface with Xtalk Minimizing Affine Signaling (XMAS), which is designed to support high-speed data transmission in die-to-die communication over silicon interposers or similar high-density interconnects susceptible to crosstalk.

Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons

no code implementations • 4 Feb 2022 • Joonghyun Song, Jiwon Shin, Hanseok Kim, Woo-Seok Choi

Due to the limitations of realizing artificial neural networks on prevalent von Neumann architectures, recent studies have presented neuromorphic systems based on spiking neural networks (SNNs) to reduce power and computational cost.