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Found 6 papers, 0 papers with code
A 4x32Gb/s 1.8pJ/bit Collaborative Baud-Rate CDR with Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution
To this end, a fractional divider controlled by CDR is placed close to the global phase locked loop.
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface with XTalk Minimizing Affine Signaling for Next-Generation HBM with High Interconnect Density
This paper presents an I/O interface with Xtalk Minimizing Affine Signaling (XMAS), which is designed to support high-speed data transmission in die-to-die communication over silicon interposers or similar high-density interconnects susceptible to crosstalk.
NeuralEQ: Neural-Network-Based Equalizer for High-Speed Wireline Communication
With the growing demand for high-bandwidth applications like video streaming and cloud services, the data transfer rates required for wireline communication keeps increasing, making the channel loss a major obstacle in achieving low bit error rate (BER).
A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-low-power Always-on Event Detection
Increasing demand for larger touch screen panels (TSPs) places more energy burden to mobile systems with conventional sensing methods.
Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons
Due to the limitations of realizing artificial neural networks on prevalent von Neumann architectures, recent studies have presented neuromorphic systems based on spiking neural networks (SNNs) to reduce power and computational cost.
Improving Spiking Neural Network Accuracy Using Time-based Neurons
Due to the fundamental limit to reducing power consumption of running deep learning models on von-Neumann architecture, research on neuromorphic computing systems based on low-power spiking neural networks using analog neurons is in the spotlight.
