NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator

1 code implementation • 23 Apr 2024 • Kaustubh Shivdikar, Nicolas Bohm Agostini, Malith Jayaweera, Gilbert Jonatan, Jose L. Abellan, Ajay Joshi, John Kim, David Kaeli

We introduce a rolling eviction strategy to mitigate data idling in on-chip memory as well as address the prevalent issue of memory bloat in sparse graph computations.

SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference

1 code implementation • 1 Oct 2021 • Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David Kaeli

In this paper we propose SECDA, a new hardware/software co-design methodology to reduce design time of optimized DNN inference accelerators on edge devices with FPGAs.

Edge-computing